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浏览/检索结果: 共7条，第1-7条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择发表日期升序发表日期降序提交时间升序提交时间降序题名升序题名降序作者升序作者降序 Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2016 Liang, Yun; Wang, Shuo 收藏  |  浏览/下载：5/0  |  提交时间：2017/12/03 register file  racetrack memory  GPU  EFFICIENT COMPILER FRAMEWORK  CACHE   Performance-centric Register File Design for GPUs using Racetrack Memory 其他 2016-01-01 Wang, Shuo; Liang, Yun; Zhang, Chao; Xie, Xiaolong; Sun, Guangyu; Liu, Yongpan; Wang, Yu; Li, Xiuhong 收藏  |  浏览/下载：5/0  |  提交时间：2017/12/03 EFFICIENT COMPILER FRAMEWORK  CACHE   Efficient GPU Spatial-Temporal Multitasking 期刊论文 ieee transactions on parallel and distributed systems, 2015 Liang, Yun; Huynh Phung Huynh; Rupnow, Kyle; Goh, Rick Siow Mong; Chen, Deming 收藏  |  浏览/下载：5/0  |  提交时间：2015/11/11 GPU  spatial  temporal  multitasking  resource allocation  OPTIMIZATION  COMPILER  MODEL   An Efficient Compiler Framework for Cache Bypassing on GPUs 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015 Liang, Yun; Xie, Xiaolong; Sun, Guangyu; Chen, Deming 收藏  |  浏览/下载：3/0  |  提交时间：2017/12/03 Cache bypassing  compiler  graphics processing unit (GPU)  performance  PROCESSORS  THROUGHPUT  MODEL  TOOL   Enabling Coordinated Register Allocation and Thread-level Parallelism Optimization for GPUs 其他 2015-01-01 Xie, Xiaolong; Liang, Yun; Li, Xiuhong; Wu, Yudong; Sun, Guangyu; Wang, Tao; Fan, Dongrui 收藏  |  浏览/下载：8/0  |  提交时间：2017/12/03 EFFICIENT COMPILER FRAMEWORK  CONTROL FLOW  CACHE  MODEL  PROCESSORS  DIVERGENCE  GPGPUS  FILE   An Efficient Compiler Framework for Cache Bypassing on GPUs 其他 2013-01-01 Xie, Xiaolong; Liang, Yun; Sun, Guangyu; Chen, Deming 收藏  |  浏览/下载：4/0  |  提交时间：2015/11/16 GPU  Cache Bypassing  Compiler Optimization   NISD: A framework for automatic narrow instruction set design 其他 2007-01-01 Liu, Xianhua; Zhang, Jiyu; Cheng, Xu 收藏  |  浏览/下载：5/0  |  提交时间：2015/11/16 dual-width instruction set  narrow instruction set design  automatic instruction set design