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清华大学 [14]

北京大学 [9]

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浏览/检索结果: 共31条，第1-10条

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	可重构高通量信号处理加速与存储接口技术研究学位论文博士, 北京: 中国科学院大学, 2018 - 收藏 \| 浏览/下载：32/0 \| 提交时间：2018/06/02 可重构计算存储器接口宽范围DLL 浮点FFT 运算加速
	Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process 期刊论文 INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2017 Wang, Yuan; Liu, Yuequan; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：8/0 \| 提交时间：2017/12/03 delay-locked loop (DLL) clock and data recovery (CDR) jitter operating range PERFORMANCE LINE
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者: Chen, Shuai; Li, Hao; Chiang, Patrick Yin 收藏 \| 浏览/下载：21/0 \| 提交时间：2019/12/13 All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
	Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics 其他 2016-01-01 Wang, Yuan; Liu, Yuequan; Jiang, Mengyin; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：3/0 \| 提交时间：2017/12/03
	A novel low-power readout structure with 1/2 sub-scan time-delay-integration and DLL-based A/D for 1024��6 infrared focal plane array 其他 2016-01-01 Liu, Benyuanyi; Lu, Wengao; Liu, Dahe; Yu, Shanzhe; Zhang, Yacong; Chen, Zhongjian 收藏 \| 浏览/下载：4/0 \| 提交时间：2017/12/03
	Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics 其他 2016-01-01 Wang, Yuan; Liu, Yuequan; Jiang, Mengyin; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：2/0 \| 提交时间：2017/12/03 quadrupler delay-locked loop (DLL) eight-phase-clock generator edge-combiner wide operating range fast locking MULTIPLIER
	A Novel Low-Power Readout Structure with 1/2 Sub-Scan Time-Delay-Integration and DLL-Based A/D for 1024x6 Infrared Focal Plane Array 其他 2016-01-01 Liu, Benyuanyi; Lu, Wengao; Liu, Dahe; Yu, Shanzhe; Zhang, Yacong; Chen, Zhongjian 收藏 \| 浏览/下载：2/0 \| 提交时间：2017/12/03 Time-delay-integration (TDI) sub-scan Infrared Focal Plane Array (IRFPA) Delay-locked-loop (DLL) Analog-to-digital converter (ADC) CMOS IMAGE SENSOR
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2 作者: Chen, Shuai; Li, Hao; Chiang, Patrick Yin 收藏 \| 浏览/下载：5/0 \| 提交时间：2019/12/13 All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
	180.5Mbps-8Gbps DLL-Based Clock and Data Recovery Circuit with Low Jitter Performance 其他 2015-01-01 Liu, Yuequan; Wang, Yuan; Jia, Song; Zhang, Xing 收藏 \| 浏览/下载：5/0 \| 提交时间：2017/12/03 Clock and data recovery (CDR) wide-range delay-locked loop (DLL) low jitter time-to-digital converter (TDC)
	A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller 期刊论文 science china information sciences, 2014 Chen HongMing; Ma Song; Wang Liu; Zhang Hao; Pan KenYi; Cheng YuHua 收藏 \| 浏览/下载：4/0 \| 提交时间：2015/11/10 all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code CMOS PROCESS PLL DLL

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