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浏览/检索结果: 共3条，第1-3条 帮助 已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 Fabrication and Characterization of Low Stress Si Interposer with Air-gapped Si Interconnection for Hermetical System-in-Package 其他 2016-01-01 Luo, Rongfeng; Ren, Kuili; Ma, Shenglin; Yan, Jun; Xia, Yanming; Jin, Yufeng; Chen, Jing; Wu, Tianzhun; Yang, Hangao; Yuan, Lifang 收藏  |  浏览/下载：5/0  |  提交时间：2017/12/03 Air-gapped Si  Si interposer  low stress  hermetical  System-in-Package  MEMS  WAFER-LEVEL  MEMS RESONATORS  TSV INTERPOSERS  VACUUM  MEMBRANES  DEVICES  SENSORS   Simulation and evaluation of thermal mechanical reliability of 3D-TSV stack with viscoelastic underfill 会议论文 Proceedings of the Electronic Packaging Technology Conference, EPTC, 2015-12-02 作者:  Zeng, Q.;  Guan, Y.;  Su, F.;  Chen, J.;  Jin, Y. 收藏  |  浏览/下载：7/0  |  提交时间：2019/12/30 Chip scale packages  Electronics packaging  Finite element method  Reliability  Thermal cycling  Viscoelasticity  Chip deformations  Relaxation modulus  Silicon interposers  Temperature dependent  Thermal-mechanical reliability  Time dependent  Viscoelastic properties  Williams-Landel-Ferry equations  Three dimensional integrated circuits   Characteristics of Coupling Capacitance Between Signal-Ground TSVs Considering MOS Effect in Silicon Interposers 期刊论文 IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015 Fang, Runiu; Sun, Xin; Miao, Min; Jin, Yufeng 收藏  |  浏览/下载：2/0  |  提交时间：2017/12/03 Coupling capacitance  MOS effect  through-silicon vias (TSVs)  THROUGH-SILICON  VIAS  TECHNOLOGY  MODEL