CORC

在结果中检索

CORC

浏览/检索结果: 共14条，第1-10条 帮助

已选(0)清除 条数/页：   排序方式：
A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication 期刊论文
2016, 2016
况立雪; 池保勇; 陈磊; 贾雯; 王志华; Kuang Lixue; Chi Baoyong; Chen Lei; Jia Wen; Wang Zhihua
收藏  |  浏览/下载：9/0
A 1.41-1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler 期刊论文
2010, 2010
Zhao, Bo; Mao, Xiaojian; Yang, Huazhong; Wang, Hui
收藏  |  浏览/下载：2/0
一种用于高速锁相环的零死区鉴频鉴相器 期刊论文
2010, 2010
屈强; 曾烈光; QU QIANG; ZENG LIEGUANG
收藏  |  浏览/下载：4/0
快速建立时间的自适应锁相环 期刊论文
2010, 2010
黄水龙; 王志华; Huang Shui-long; Wang Zhi-hua
收藏  |  浏览/下载：3/0
A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector 会议论文
9th international conference on solid-state and integrated-circuit technology, beijing, peoples r china, oct 20-23, 2008
Liu, SL; Hao, ZK; Ma, HP; Yuan, L; Shi, Y
收藏  |  浏览/下载：35/0  |  提交时间：2010/03/09
PLL  
Study of Digital Video Interface (DVI) architecture design in computer system 会议论文
作者:  Bai, Xiaoping;  Zhang, Hongwei
收藏  |  浏览/下载：2/0  |  提交时间：2019/12/18
A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and cmos transistors 期刊论文
Ieee transactions on circuits and systems i-regular papers, 2007, 卷号: 54, 期号: 11, 页码: 2516-2527
作者:  Zhang, Wancheng;  Wu, Nan-Han
收藏  |  浏览/下载：45/0  |  提交时间：2019/05/12
Design of the fast aequisition PLL with wide tuning range 其他
2007-01-01
Yan, Ge; Song, Jia; Lijiu, Ji
收藏  |  浏览/下载：2/0  |  提交时间：2015/11/13
Fast acquisition PLL with wide tuning range 期刊论文
pan tao ti hsueh paochinese journal of semiconductors, 2007
Ge, Yan; Jia, Song; Ye, Hongfei; Ji, Lijiu
收藏  |  浏览/下载：5/0  |  提交时间：2015/11/13
A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors 期刊论文
ieee transactions on circuits and systems i-regular papers, 2007, 卷号: 54, 期号: 11, 页码: 2516-2527
Zhang WC (Zhang Wancheng); Wu NH (Wu Nan-Han)
收藏  |  浏览/下载：77/0  |  提交时间：2010/03/29

©版权所有 ©2017 CSpace - Powered by CSpace