低功耗设计技术在SoC中的研究与应用

CORC > 沈阳自动化研究所 > 中国科学院沈阳自动化研究所 > 工业信息学研究室 > 工业控制系统研究室

题名	低功耗设计技术在SoC中的研究与应用
作者	董策
学位类别	硕士
答辩日期	2005-05-31
授予单位	中国科学院沈阳自动化研究所
授予地点	中国科学院沈阳自动化研究所
导师	杨志家
关键词	SoC 低功耗功耗分析功耗优化
其他题名	The Research and Application of Low-Power Design Techniques in SoC
学位专业	机械电子工程
中文摘要	从芯片层次上看，功耗是一个关键参数。现代的系统芯片（SoC）除了规模很大和工作速度很快外，通常还必须在低功率条件下进行设计。尤其对于依靠电池来工作的芯片，低功耗设计是非常有必要的。本文在详细分析了CMOS管的功耗特性的基础上，从全定制与基于标准单元的可综合方法上，从系统到版图的各设计层次上，从功能设计到物理设计的各设计阶段上，全面研究和总结了SoC低功耗设计技术。尤其针对设计中常遇到的问题，提出了相应的解决方案。然后提出了一整套基于深亚微米设计平台的功耗验证、优化的流程和方法，这种方法是通过仿真、分析和优化来实现设计中对低功耗的需求，同时还分析了两种重要的高层次功耗优化技术：RTL门控时钟和算子隔离。使用该流程和方法，对系统芯片（FF_SoC）和专用芯片（FF_H1）进行了功耗验证和优化，取得很好的应用效果。最后，本文完成了AES加密算法的从RTL到netlist的实现，在 0.18μm工艺下，最高工作频率410MHz，数据吞吐率5.23Gbps，功耗58mW。设计中使用了本文提到的设计流程和方法进行功耗优化。本文的创新之处和应用价值可概括为以下几个方面： 1)从SoC设计方法、层次、流程上全面研究和总结了低功耗设计技术，尤其针对设计中常遇到的问题，提出了相应的解决方案。遵循这些方案，设计者可以避免许多类似问题的发生，有利于SoC低功耗设计的快速实现。 2)开发、示范和总结出一套基于深亚微米设计平台的功耗验证、优化流程，它是作者在参与SoC设计过程中总结出来的最有效的方法。在RTL和门级都可以进行功耗的优化，优化所处层次越高，优化效果越好。在整个设计流程的早期，通过RTL仿真进行初步的功耗估计，可以对功耗、面积、速度进行折中选择（选择不同的结构和代码风格）；在逻辑门级，通过门级仿真进行功耗分析，可以对芯片电源网络的初步布局和内核供电压焊块（pad）的选择、摆放提供重要的指导；对布线后的网表，也可通过门级仿真获得最精确的功耗分析结果。 3)独立完成了AES加密算法的从RTL到netlist的实现，设计中采用改进算法（T盒算法），将轮变换操作中的不同步骤合并为一组表的查询，有效降低了关键时序路径的传输延迟，并通过动态功耗管理和门控时钟等低功耗设计技术有效地降低了功耗。
索取号	TN492/D65/2005
英文摘要	Power consumption is critical at the chip level. Beyond being large and fast, modern SoC must frequently be designed for low power consumption. Low-power design is of course critical for battery-operated devices. In this dessertation, first we describe power characteristics of CMOS circuits. Second, we study the low-power design techniques at SoC design methodology, full-custom design vs. synthesis-based standard cell design; at every level of abstraction, from system architecture down to layout; at every phase of design flow, from functional design down to physical design. Third, we present a methodology of power analysis and optimization based on deep submicron design platform, and we introduce two important high-level techniques for reducing power consumption: RTL clock gating and operand isolation. Finally, we implement a high-speed, low-power AES design from RTL to gate-level netlist. In 0.18μm CMOS technology of VeriSilicon and with Synopsys design flow, the design runs at 410MHz resulting in a throughput of 5.23Gbps while consuming 58mW. Several low-power techniques, such as power management and clock gating, are well applied for power optimization. The main contributions and innovations of this dissertation can be described as following: 1)The author does much research on low-power design techniques at every level and phase of SoC design cycle and proposes corresponding discipline to solve problems in low power SoC design cycle. Following the discipline, IC designers can avoid similar problems. The discipline can help make the design iterations as few and quick as possible; 2)The author develops, demonstrates, and summarizes a methodology of power analysis and optimization based on deep submicron design platform. The design methodology works best for designing low power chips. We can analyze and optimize at the RTL and gate level. Early in design cycle, we can use power analysis with switching activity from RTL simulation to obtain quick results and explore design tradeoffs. At gate-level, we can direct an initial route of the power mesh, the distribution of power and ground in the chip. It is also helpful to the placement of power supply pad for core logic. Later in design cycle, we can use the accuracy of gate-level simulation to annotate specific nets of your design or all the elements and power analysis is most accurate; 3)The author implements a high-speed, low-power AES design from RTL to netlist. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is used for reducing the delay of critical data path. And several low-power techniques, such as power management and clock gating, are well applied for power optimization.
语种	中文
产权排序	1
公开日期	2012-08-29
分类号	TN492
内容类型	学位论文
源URL	[http://ir.sia.ac.cn/handle/173321/9455]
专题	沈阳自动化研究所_工业信息学研究室_工业控制系统研究室
推荐引用方式 GB/T 7714	董策. 低功耗设计技术在SoC中的研究与应用[D]. 中国科学院沈阳自动化研究所. 中国科学院沈阳自动化研究所. 2005.