An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

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	An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process
	Li, YL (Li, Y-L.) ; Feng, P (Feng, P.) ; Wu, NJ (Wu, N-J.)
	2008
会议名称	ieee international conference of electron devices and solid-state circuits
会议日期	dec 08-10, 2008
会议地点	hong kong, peoples r china
关键词	VOLTAGE
页码	100-103
通讯作者	li, yl, chinese acad sci, state key lab superlattices & microstruct, inst semicond, beijing 100864, peoples r china.
中文摘要	this paper proposes an embedded ultra low power nonvolatile memory in a standard cmos logic process. the memory adopts a bit cell based on the differential floating gate pmos structure and a novel operating scheme. it can greatly improve the endurance and retention characteristic and make the area/bit smaller. a new high efficiency all-pmos charge pump is designed to reduce the power consumption and to increase the power efficiency. it eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. a 32-bit prototype chip is fabricated in a 0.18 mu m 1p4m standard cmos logic process and the core area is 0.06 mm(2). the measured results indicate that the typical write/erase time is 10ms. with a 700 khz clock frequency, power consumption of the whole memory is 2.3 mu a for program and 1.2 mu a for read at a 1.6v power supply.
英文摘要	this paper proposes an embedded ultra low power nonvolatile memory in a standard cmos logic process. the memory adopts a bit cell based on the differential floating gate pmos structure and a novel operating scheme. it can greatly improve the endurance and retention characteristic and make the area/bit smaller. a new high efficiency all-pmos charge pump is designed to reduce the power consumption and to increase the power efficiency. it eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. a 32-bit prototype chip is fabricated in a 0.18 mu m 1p4m standard cmos logic process and the core area is 0.06 mm(2). the measured results indicate that the typical write/erase time is 10ms. with a 700 khz clock frequency, power consumption of the whole memory is 2.3 mu a for program and 1.2 mu a for read at a 1.6v power supply.; zhangdi于2010-03-09批量导入; made available in dspace on 2010-03-09t07:08:21z (gmt). no. of bitstreams: 1 728.pdf: 737043 bytes, checksum: 1b2584c56a2d686e41a393c9aacae23b (md5) previous issue date: 2008; ieee.; [li, y-l.; feng, p.; wu, n-j.] chinese acad sci, state key lab superlattices & microstruct, inst semicond, beijing 100864, peoples r china
收录类别	CPCI-S
会议主办者	ieee.
会议录	edssc: 2008 ieee international conference on electron devices and solid-state circuits
会议录出版者	ieee ; 345 e 47th st, new york, ny 10017 usa
会议录出版地	345 e 47th st, new york, ny 10017 usa
学科主题	微电子学
语种	英语
ISBN号	978-1-4244-2539-6
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/8368]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Li, YL ,Feng, P ,Wu, NJ . An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process[C]. 见:ieee international conference of electron devices and solid-state circuits. hong kong, peoples r china. dec 08-10, 2008.