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	A Computing Efficient Hardware Architecture for Sparse Deep Neural Network Computing
	Zhang, Y.; Ouyang, P.; Yin, S.; Zhao, W.; Wei, S.
	2018
会议名称	2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
关键词	Integrated circuits Memory architecture Network architecture Neural networks Convolutional neural network Dataflow Hardware architecture Load imbalance Memory consumption State of the art State-of-the-art performance Switching strategies Deep neural networks
URL标识	查看原文
内容类型	会议论文
URI标识	http://www.corc.org.cn/handle/1471x/5925917
专题	北京航空航天大学
推荐引用方式 GB/T 7714	Zhang, Y.,Ouyang, P.,Yin, S.,et al. A Computing Efficient Hardware Architecture for Sparse Deep Neural Network Computing[C]. 见:2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings.

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