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	An STT-MRAM Based in Memory Architecture for Low Power Integral Computing
	Zhao, Yinglin; Ouyang, Peng; Kang, Wang; Yin, Shouyi; Zhang, Youguang; Wei, Shaojun; Zhao, Weisheng
刊名	IEEE TRANSACTIONS ON COMPUTERS
	2019
卷号	68页码:617-623
关键词	Integral histogram parallel architecture STT-MRAM processing in memory full adder
ISSN号	0018-9340
DOI	10.1109/TC.2018.2879502
URL标识	查看原文
收录类别	SCIE ; EI
WOS记录号	WOS:000461236900012
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5921183
专题	北京航空航天大学
推荐引用方式 GB/T 7714	Zhao, Yinglin,Ouyang, Peng,Kang, Wang,et al. An STT-MRAM Based in Memory Architecture for Low Power Integral Computing[J]. IEEE TRANSACTIONS ON COMPUTERS,2019,68:617-623.
APA	Zhao, Yinglin.,Ouyang, Peng.,Kang, Wang.,Yin, Shouyi.,Zhang, Youguang.,...&Zhao, Weisheng.(2019).An STT-MRAM Based in Memory Architecture for Low Power Integral Computing.IEEE TRANSACTIONS ON COMPUTERS,68,617-623.
MLA	Zhao, Yinglin,et al."An STT-MRAM Based in Memory Architecture for Low Power Integral Computing".IEEE TRANSACTIONS ON COMPUTERS 68(2019):617-623.

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