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	Hardware Acceleration Implementation of Sparse Coding Algorithm With Spintronic Devices
	Zhang, Deming; Hou, Yanchun; Zeng, Lang; Zhao, Weisheng
刊名	IEEE TRANSACTIONS ON NANOTECHNOLOGY
	2019
卷号	18页码:518-531
关键词	Sparse coding MTJ DWM hardware acceleration neuromorphic computing parallelization multiple conductance states cross-point array artificial neural network (ANN)
ISSN号	1536-125X
DOI	10.1109/TNANO.2019.2916149
URL标识	查看原文
收录类别	SCIE ; EI
WOS记录号	WOS:000469366400002
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5919154
专题	北京航空航天大学
推荐引用方式 GB/T 7714	Zhang, Deming,Hou, Yanchun,Zeng, Lang,et al. Hardware Acceleration Implementation of Sparse Coding Algorithm With Spintronic Devices[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY,2019,18:518-531.
APA	Zhang, Deming,Hou, Yanchun,Zeng, Lang,&Zhao, Weisheng.(2019).Hardware Acceleration Implementation of Sparse Coding Algorithm With Spintronic Devices.IEEE TRANSACTIONS ON NANOTECHNOLOGY,18,518-531.
MLA	Zhang, Deming,et al."Hardware Acceleration Implementation of Sparse Coding Algorithm With Spintronic Devices".IEEE TRANSACTIONS ON NANOTECHNOLOGY 18(2019):518-531.

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