A single event upset hardened flip-flop design utilizing layout technique

doi:10.1016/j.microrel.2019.113496

	A single event upset hardened flip-flop design utilizing layout technique
	Wang, Haibin 5; Chu, Jiamin 5; Wei, Jinghe 4; Shi, Junwei 3; Sun, Hongwen 5; Han, Jianwei 2; Qian, Rong 1
刊名	Microelectronics Reliability
	2019
卷号	102
ISSN号	0026-2714
DOI	10.1016/j.microrel.2019.113496
英文摘要	A novel Quatro-based flip-flop design with low penalty was proposed. By utilizing layout technique, SEU hardness was achieved in this design because of charge sharing between the introduced PMOS transistors. Both the proposed design and the reference flip-flop were fabricated in a 65 nm standard CMOS technology. The pulsed laser experiment results demonstrate that the new design has a larger upset threshold and lower SEU error rate compared with the reference. The area and delay penalties are not significant, i.e., 13% and 37%, respectively. © 2019 Elsevier Ltd
语种	英语
内容类型	期刊论文
源URL	[http://ir.nssc.ac.cn/handle/122/7179]
专题	国家空间科学中心_空间技术部
作者单位	1.Jiangsu Jotry Electrical Technology Co. Ltd, Changzhou; Jiangsu; 213100, China 2.National Space Science Center, Beijing; 101499, China; 3.Changzhou Taiping Communication Technology Co. Ltd, Changzhou; Jiangsu; 213022, China; 4.No.58 Research Institute, China Electronics Technology Group Corporation, Wuxi; Jiangsu; 214035, China; 5.College of IoT Engineering, Hohai University, Changzhou; Jiangsu; 213022, China;
推荐引用方式 GB/T 7714	Wang, Haibin,Chu, Jiamin,Wei, Jinghe,et al. A single event upset hardened flip-flop design utilizing layout technique[J]. Microelectronics Reliability,2019,102.
APA	Wang, Haibin.,Chu, Jiamin.,Wei, Jinghe.,Shi, Junwei.,Sun, Hongwen.,...&Qian, Rong.(2019).A single event upset hardened flip-flop design utilizing layout technique.Microelectronics Reliability,102.
MLA	Wang, Haibin,et al."A single event upset hardened flip-flop design utilizing layout technique".Microelectronics Reliability 102(2019).