Retention-Aware DRAM Assembly and Repair for Future FGR Memories

doi:10.1109/TCAD.2016.2597220

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	Retention-Aware DRAM Assembly and Repair for Future FGR Memories
	Wang, Ying; Han, Yin-He; Wang, Cheng; Li, Huawei; Li, Xiaowei
刊名	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
	2017-05-01
卷号	36 期号:5 页码:705-718
关键词	DDR dynamic random-access memory (DRAM) memory refresh
ISSN号	0278-0070
DOI	10.1109/TCAD.2016.2597220
英文摘要	Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh- oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the "compatible" devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subar-ray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.
资助项目	National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61176040] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61402146] ; National Natural Science Foundation of China[61521092] ; National Science and Technology Major Project[2013ZX0102-8001-001-001]
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000399944100001
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/6937]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, Huawei
作者单位	Chinese Acad Sci, State Key Lab Comp Architecture, Inst Comp Technol, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Han, Yin-He,Wang, Cheng,et al. Retention-Aware DRAM Assembly and Repair for Future FGR Memories[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2017,36(5):705-718.
APA	Wang, Ying,Han, Yin-He,Wang, Cheng,Li, Huawei,&Li, Xiaowei.(2017).Retention-Aware DRAM Assembly and Repair for Future FGR Memories.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,36(5),705-718.
MLA	Wang, Ying,et al."Retention-Aware DRAM Assembly and Repair for Future FGR Memories".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 36.5(2017):705-718.