Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips

doi:10.1109/TVLSI.2017.2682885

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips
	Wang, Ying; Deng, Jiachao; Fang, Yuntan; Li, Huawei; Li, Xiaowei
刊名	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
	2017-10-01
卷号	25 期号:10 页码:2736-2748
关键词	Deep learning error tolerance neural network (NN) timing variation
ISSN号	1063-8210
DOI	10.1109/TVLSI.2017.2682885
英文摘要	Unlike conventional ICs, approximate computing chips are less sensitive to hardware errors. This fascinating feature can be utilized to improve the performance of chip design and even change the timing closure procedure of digital circuit design flow. In this paper, we study the potential of resilience-aware circuit clocking scheme, and demonstrate the methodology with advanced neural network (NN)-based accelerator. We propose a novel timing analysis and frequency setting method for NN-based approximate computing circuits based on in-field NN retraining. With the proposed iterative retiming-and-retraining framework, NN-based accelerator can be retrained to operate safely at aggressive operating frequencies compared with the frequency decided purely by statistical timing analysis or Monto Carlo analysis. For nanometer process technology with increasing threats of timing errors induced by process variation, noises, and so on, our retiming-and-retraining method enables higher circuit operating frequency and enables dynamic precision/frequency adjustment for approximate computing circuits. We evaluate the methodology with both the neural and deep learning accelerators in experiments. The experimental results show that timing errors in neural circuits can be effectively tamed for different applications, so that the circuits can operate at higher clocking rates under the specified quality constraint or be dynamically scaled to work at a wide range of frequency states with only minor accuracy losses.
资助项目	National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61532017] ; National Natural Science Foundation of China[61572470] ; National Natural Science Foundation of China[61402146] ; National Natural Science Foundation of China[61521092] ; National Science and Technology Major Project[2013ZX0102-8001-001-001]
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000413751500006
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/6475]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang, Ying; Li, Huawei
作者单位	Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Deng, Jiachao,Fang, Yuntan,et al. Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25(10):2736-2748.
APA	Wang, Ying,Deng, Jiachao,Fang, Yuntan,Li, Huawei,&Li, Xiaowei.(2017).Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25(10),2736-2748.
MLA	Wang, Ying,et al."Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25.10(2017):2736-2748.