晶体管及其制造方法 | |
朱慧珑![]() ![]() ![]() | |
2014-03-19 | |
著作权人 | 中国科学院微电子研究所 |
专利号 | GB2489067 |
国家 | 英国 |
文献子类 | 发明专利 |
英文摘要 | A transistor includes: a substrate (100) with a channel region; a source region (101) and a drain region (102) on opposite ends of the channel region of the substrate (100); a high-k gate dielectric layer (103) on the top surface of the substrate (100) above the channel region between the source region (101) and the drain region (102); an interface layer under the high-k gate dielectric layer (103), a first portion (107) thereof close to the source region (101), a second portion (106) thereof close to the drain region (102), the equivalent oxide thickness of the first portion (107) is greater than that of the second portion (106). An asymmetric interface layer caused by a dual material asymmetric gate can help suppress the short channel effect at the drain side and avoid decreasing the mobility of carriers at the source side. In addition, the asymmetric gate can have different work functions. |
公开日期 | 2012-09-19 |
申请日期 | 2010-06-28 |
语种 | 中文 |
内容类型 | 专利 |
源URL | [http://10.10.10.126/handle/311049/13300] ![]() |
专题 | 微电子研究所_集成电路先导工艺研发中心 |
作者单位 | 中国科学院微电子研究所 |
推荐引用方式 GB/T 7714 | 朱慧珑,骆志炯,尹海洲. 晶体管及其制造方法. GB2489067. 2014-03-19. |
个性服务 |
查看访问统计 |
相关权益政策 |
暂无数据 |
收藏/分享 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论