EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model

doi:10.1007/s11704-017-6279-2

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model
	Ruan, Li 4,5; He, Zhenxue 4,5,6; Xiao, Limin 4,5; Gu, Fei 4; Huo, Zhisheng 4,5; Li, Mingzhe 3; Zhu, Mingfa 4,5; Zhang, Longbing 2; Liu, Rui 1; Wang, Xiang 3
刊名	FRONTIERS OF COMPUTER SCIENCE
	2019-10-01
卷号	13 期号:5 页码:1102-1115
关键词	delay optimization mixed-polarity Reed-Muller logic circuits unit delay model don't-care terms Huffman tree construction algorithm
ISSN号	2095-2228
DOI	10.1007/s11704-017-6279-2
英文摘要	Delay optimization has recently attracted significant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay optimization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is obtained using a novel Reed-Muller expression simplification approach (RMESA) considering don't-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplest MPRM expression. Experimental results on MCNC benchmark circuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most circuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.
资助项目	National Natural Science Foundation of China[61370059] ; National Natural Science Foundation of China[61232009] ; Beijing Natural Science Foundation[4152030] ; Fundamental Research Funds for the Central Universities[YWF-15-GJSYS-085] ; Fundamental Research Funds for the Central Universities[YWF-14-JSJXY-14] ; Open Project Program of National Engineering Research Center for Science & Technology Resources Sharing Service (Beihang University) ; fund of the State Key Laboratory of Computer Architecture[CARCH201507] ; fund of the State Key Laboratory of Software Development Environment[SKLSDE-2016ZX-13]
WOS研究方向	Computer Science
语种	英语
出版者	HIGHER EDUCATION PRESS
WOS记录号	WOS:000471933400014
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/4181]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Xiao, Limin
作者单位	1.Natl Engn Res Ctr Sci & Technol Resources Sharing, Beijing 100083, Peoples R China 2.Chinese Acad Sci, State Key Lab Comp Architecture, Inst Comp Technol, Beijing 100190, Peoples R China 3.Beihang Univ, Sch Elect & Informat Engn, Beijing 100083, Peoples R China 4.Beihang Univ, Sch Comp Sci & Engn, Beijing 100083, Peoples R China 5.Beihang Univ, State Key Lab Software Dev Environm, Beijing 100083, Peoples R China 6.Hebei Univ, Sch Cyber Secur & Comp, Baoding 071002, Peoples R China
推荐引用方式 GB/T 7714	Ruan, Li,He, Zhenxue,Xiao, Limin,et al. EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model[J]. FRONTIERS OF COMPUTER SCIENCE,2019,13(5):1102-1115.
APA	Ruan, Li.,He, Zhenxue.,Xiao, Limin.,Gu, Fei.,Huo, Zhisheng.,...&Wang, Xiang.(2019).EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model.FRONTIERS OF COMPUTER SCIENCE,13(5),1102-1115.
MLA	Ruan, Li,et al."EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model".FRONTIERS OF COMPUTER SCIENCE 13.5(2019):1102-1115.