QQ客服 官方微博 反馈留言

	Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell
	Xu, Zhaozhao; Liu, Donghua; Hu, Jun; Chen, Wenjie; Qian, Wensheng; Kong, Weiran; Zou, Shichang
刊名	Solid-State Electronics
	2019
卷号	152页码:46-52
关键词	2-bit/cell Device-scaling Drain induced barrier lowering effects Source-side injection Split gates
ISSN号	0038-1101
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2827647
专题	西安交通大学
推荐引用方式 GB/T 7714	Xu, Zhaozhao,Liu, Donghua,Hu, Jun,et al. Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell[J]. Solid-State Electronics,2019,152:46-52.
APA	Xu, Zhaozhao.,Liu, Donghua.,Hu, Jun.,Chen, Wenjie.,Qian, Wensheng.,...&Zou, Shichang.(2019).Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell.Solid-State Electronics,152,46-52.
MLA	Xu, Zhaozhao,et al."Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell".Solid-State Electronics 152(2019):46-52.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。