Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From   Device to System

doi:10.1109/TCSI.2016.2529240

CORC > 北京大学 > 信息科学技术学院

	Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System
	Zhang, Yue ; Zhang, Chao ; Nan, Jiang ; Zhang, Zhizhong ; Zhang, Xueying ; Klein, Jacques-Olivier ; Ravelosona, Dafine ; Sun, Guangyu ; Zhao, Weisheng
刊名	IEEE International Symposium on Circuits and Systems (ISCAS)
	2016
关键词	Chiral domain wall motion L2 cache magnetic field assistance racetrack memory DOMAIN-WALL MOTION ELECTRIC-FIELD CONTROL FERROMAGNETIC NANOWIRES TORQUE
DOI	10.1109/TCSI.2016.2529240
英文摘要	Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption.; SCI(E); EI; ARTICLE; 5; 629-638; 63
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/494679]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhang, Yue,Zhang, Chao,Nan, Jiang,et al. Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System[J]. IEEE International Symposium on Circuits and Systems (ISCAS),2016.
APA	Zhang, Yue.,Zhang, Chao.,Nan, Jiang.,Zhang, Zhizhong.,Zhang, Xueying.,...&Zhao, Weisheng.(2016).Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.IEEE International Symposium on Circuits and Systems (ISCAS).
MLA	Zhang, Yue,et al."Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System".IEEE International Symposium on Circuits and Systems (ISCAS) (2016).