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	A 1.8-V 12-bit self-calibrating SAR ADC with a novel comparator
	Deng, Chenxi ; Zhao, Long ; Zheng, Hui ; Cheng, Yuhua
	2015
英文摘要	A 1.8-V 12-bit fully differential self-calibrating SAR ADC is presented in a standard 0.18��m CMOS technology. To improve the SNDR and achieve a low core area, it adapts a capacitive self-calibrating method. The way to estimate the calibration range is discussed. Based on a minimizing capacitance principle, a novel comparator is proposed to enhance speed and save power. At the speed of 6 MS/s, the ADC achieves 11.3 ENOB by Spectre simulation, with estimated comparator offset of 30mV and unit capacitor mismatch of 4% sigma. It consumes 839 ��W for the analog part. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517009
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449308]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Deng, Chenxi,Zhao, Long,Zheng, Hui,et al. A 1.8-V 12-bit self-calibrating SAR ADC with a novel comparator. 2015-01-01.

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