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	A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier
	Chen, Jiyu ; Jia, Song ; Wang, Yuan
	2015
英文摘要	This paper presents a TA based coarse-fine TDC with high resolution. The new design contains a half-pass judger to measure the relative position of the stop edge in the subrange of the delayed sequence. The extra operation helps to limit the range of time residue sent to the fine stage by one half. With the limitation, TA can achieve a high gain, ensuring the two-stage TDC with a high resolution. Besides, a new MUX structure is designed, and the signal ports are well arranged to improve the reaction speed and to reduce the power consumption. Experiment results show that resolution of the proposed circuit is 0.7ps, and the measurement range can reach 1ns. The DNL and INL are measured as 0.5LSB and 2LSB, respectively. Better linearity can be achieved by using INL lookup table and adding compensated blocks. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517126
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449307]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Chen, Jiyu,Jia, Song,Wang, Yuan. A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. 2015-01-01.

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