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	A Wafer Level Through-Stack-Via Integration Process with One-time Bottom-up Copper Filling
	Zhu, Yunhui ; Ma, Shenglin ; Sun, Xin ; Fang, Runiu ; Zhong, Xiao ; Bian, Yuan ; Guan, Yong ; Chen, Jing ; Miao, Min ; Jin, Yufeng
	2014
关键词	INTERCONNECTS
英文摘要	We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using one-time bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned from backside to reveal the TSVs. The carrier wafer was coated with a release layer and a seed layer, which provided a uniform seed layer for bottom-up TSV filling and was easy to be debonded. A layer of copper RDL was pre-deposited on the silicon wafer before bonding, which enhanced the wettability of the sidewall of TSVs during bottom-up copper filling. More silicon wafers could be bonded and thinned in the same way. At last, one-time bottom-up TSV filling was performed and the carrier wafer was released. A 4-layer wafer stacking with TSVs of 173 mu m x 52 mu m has been successfully demonstrated with the thinnest wafer of 22 mu m. The electrical test results shown that this process had a significant yield improvement. The lowest resistance measured was 7.6m Omega with the yield of over 84% on the 4-inch wafer. This proposed TSV integration process was ready for stacked memory application.; EI; CPCI-S(ISTP); j.chen@pku.edu.cn; 1902-1907
语种	英语
出处	2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)
DOI标识	10.1109/ECTC.2014.6897561
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/424014]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhu, Yunhui,Ma, Shenglin,Sun, Xin,et al. A Wafer Level Through-Stack-Via Integration Process with One-time Bottom-up Copper Filling. 2014-01-01.

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