Instruction Cache Locking Using Temporal Reuse Profile

doi:10.1109/TCAD.2015.2418320

CORC > 北京大学 > 信息科学技术学院

	Instruction Cache Locking Using Temporal Reuse Profile
	Liang, Yun ; Mitra, Tulika ; Ju, Lei
刊名	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
	2015
关键词	Cache cache locking performance temporal reuse profile (TRP) REAL-TIME SYSTEMS EMBEDDED SYSTEMS MULTI-CORES
DOI	10.1109/TCAD.2015.2418320
英文摘要	The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the performance of an application. Modern embedded processors often feature cache locking mechanisms that allow memory blocks to be locked in the cache under software control. Cache locking was primarily designed to offer timing predictability for hard real-time applications. Hence, prior techniques focus on employing cache locking to improve the worst-case execution time. However, cache locking can be quite effective in improving the average-case execution time of general embedded applications as well. In this paper, we explore static instruction cache locking to improve the average-case program performance. We introduce temporal reuse profile (TRP) to accurately and efficiently model the cost and benefit of locking memory blocks in the cache. We consider two locking mechanisms, line locking and way locking. For each locking mechanism, we propose a branch-and-bound algorithm and a heuristic approach that use the TRP to determine the most beneficial memory blocks to be locked in the cache. Experimental results show that the heuristic approach achieves close to the results of branch-and-bound algorithm and can improve the performance by 12% on average for 4 KB cache across a suite of real-world benchmarks. Moreover, our heuristic provides significant improvement compared to the state-of-the-art locking algorithm both in terms of performance and efficiency.; National Natural Science Foundation of China [61300005, 61202015]; Singapore Ministry of Education Academic Research Fund Tier 1 [T1-251RES1120]; SCI(E); EI; ARTICLE; ericlyun@pku.edu.cn; 9; 1387-1400; 34
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/416850]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Liang, Yun,Mitra, Tulika,Ju, Lei. Instruction Cache Locking Using Temporal Reuse Profile[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2015.
APA	Liang, Yun,Mitra, Tulika,&Ju, Lei.(2015).Instruction Cache Locking Using Temporal Reuse Profile.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
MLA	Liang, Yun,et al."Instruction Cache Locking Using Temporal Reuse Profile".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2015).