QQ客服 官方微博 反馈留言

	Design and process development of a stacked SRAM memory chip module with TSV interconnection
	Ma, Shenglin ; Sun, Xin ; Zhu, Yunhui ; Zhu, Zhiyuan ; Cui, Qinghu ; Chen, Meng ; Xiao, Yongqiang ; Chen, Jing ; Miao, Min ; Lu, Wengao ; Jin, Yufeng
	2012
英文摘要	In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, there's no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper electroplating while the ones on the backside will be formed with backside releasing process. A test run is carried out with this novel process and a 4-layer stacked chip module is successfully fabricated. ? 2012 IEEE.; EI; 2
语种	英语
DOI标识	10.1109/ECTC.2012.6249101
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/412240]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Ma, Shenglin,Sun, Xin,Zhu, Yunhui,et al. Design and process development of a stacked SRAM memory chip module with TSV interconnection. 2012-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。