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	An improved test access mechanism structure and optimization technique in system-on-chip
	Feng Jianhua ; Long Jieyi ; Xu Wenhua ; Ye Hongfei
	2005
英文摘要	This paper presents a new test access mechanism (TAM) architecture and optimization method based on an improved flexible-width test bus. The method is first to set up the test time lower bound that is not depends on TAM architecture, then to construct a bus assignment that makes test time up to the lower bound. We present experimental results on our improved flexible-width test buses for four benchmark SOCs. Experiment results in a significant reduction of the test time, and is better than the proposed traditional methods in test time.; Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/406758]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Feng Jianhua,Long Jieyi,Xu Wenhua,et al. An improved test access mechanism structure and optimization technique in system-on-chip. 2005-01-01.

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