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	Bitwidth-aware scheduling and binding in high-level synthesis
	Cong, Jason ; Fan, Yiping ; Han, Guoling ; Lin, Yizhou ; Xu, Junjuan ; Zhang, Zhiru ; Cheng, Xu
	2005
英文摘要	Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifications without bitwidth analysis may introduce wasted resources. Furthermore, conventional high-level synthesis techniques usually focus on uniform-width resources, thus they cannot obtain the full resource savings even with bitwidth information. This work develops a bitwidth-aware synthesis flow, including bitwidth analysis, scheduling and binding, and register allocation and binding, to exploit the multi-birwidth nature of operations and variables for area-efficient designs. We also develop lower bound estimation to evaluate the efficiency of our proposed solutions for register allocation and binding. The flow is implemented in the MCAS synthesis system [11]. Experimental results show that our proposed bitwidth-aware synthesis flow reduces area by 36% and wire-length by 52% on average compared to the uniform-width MCAS flow, while achieving the same performance. ? 2005 IEEE.; EI; 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/328255]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Cong, Jason,Fan, Yiping,Han, Guoling,et al. Bitwidth-aware scheduling and binding in high-level synthesis. 2005-01-01.

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