QQ客服 官方微博 反馈留言

	A low power high speed readout circuit for 320 �� 320 IRFPA
	Wang, Guannan ; Lu, Wengao ; Fang, Ran ; You, Li ; Zhang, Yacong ; Chen, Zhongjian ; Ji, Lijiu
	2011
英文摘要	A low power high speed Readout Integrated Circuit(ROIC) design for 320 ?? 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 ?? 320 ROIC with pixel size of 30 ?? 30 ??m2 has been designed and fabricated with a 0.35 ??m DPTM CMOS process under 5v supply voltage. ? 2011 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/EDSSC.2011.6117610
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/294877]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wang, Guannan,Lu, Wengao,Fang, Ran,et al. A low power high speed readout circuit for 320 �� 320 IRFPA. 2011-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。