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	A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC
	Cao Junmin ; Chen Zhongjian ; Lu Wengao ; Zhao Baoying
	2008
关键词	CMOS ADC 10-BIT
英文摘要	A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp, during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1 dB with a 1MHz full-scale sine input at 20MS/s.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000265971003014&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293445]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Cao Junmin,Chen Zhongjian,Lu Wengao,et al. A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC. 2008-01-01.

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