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	A 1.25/2.5/3.125Gbps CDR circuit with a phase interpolator for RapidIO application
	Yang, Hailing ; Wang, Yuan ; Jia, Song ; Zhang, Ganggang ; Zhang, Xing
	2012
关键词	clock and data recovery phase interpolator current mode logic adaptive bandwidth PLL CLOCK
英文摘要	A phase interpolator (PI)-based clock data recovery (CDR) circuit for RapidIO application is presented, which avoids the coupled interference of VCOs. With the integration of a digital control cell, the complex and area consumption has been reduced effectively. An adaptive bandwidth PLL structure is adopted so that it can provide clocks of three frequencies while maintain a good jitter performance. In a 0.13um CMOS process, the circuit has a jitter of 11.2ps@3.125Gbps with a power consumption of 21.7mW under 1.2V, and the core circuit area is 0.16mm(2).; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000319824700299&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/292719]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yang, Hailing,Wang, Yuan,Jia, Song,et al. A 1.25/2.5/3.125Gbps CDR circuit with a phase interpolator for RapidIO application. 2012-01-01.

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