Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon   Nanowire MOSFETs

doi:10.1109/TED.2010.2065808

CORC > 北京大学 > 信息科学技术学院

	Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs
	Yu, Tao ; Wang, Runsheng ; Huang, Ru ; Chen, Jiang ; Zhuge, Jing ; Wang, Yangyuan
刊名	ieee电子器件汇刊
	2010
关键词	Intrinsic parameter fluctuation line-edge roughness (LER) silicon nanowire MOSFET (SNWT) variability INTRINSIC PARAMETER FLUCTUATIONS FINFET MATCHING PERFORMANCE CARRIER TRANSPORT CMOS TECHNOLOGY IMPACT TRANSISTORS DEVICES DECANANOMETER VARIABILITY INTEGRATION
DOI	10.1109/TED.2010.2065808
英文摘要	In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which allows the nanowire edges to vary in arbitrary transverse direction and which is different from the LER in traditional devices with one degree of freedom. In order to identify the relative importance of the diameter and center position variations, the nanowire LER can be considered as the combination of two basic types: One has a varied diameter with a fixed center (type A), and the other has a varied center position with a fixed diameter (type B). The results indicate the tradeoff between these two types of LER, with type A of a larger performance variation and type B of a larger performance degradation. Furthermore, as the gate length L(g) shrinks below the correlation length. of the nanowire LER, the impacts from the source/drain extension region will dominate the variation. The impact of the main LER parameters is discussed for the scaled case with a nonGaussian distribution in the device electrical parameters observed, and a new statistical method is proposed for better evaluation. On the other hand, the performance variation becomes insensitive to the correlation length in the case of Lambda > L(g), which indicates a higher tolerance for the nanowire LER design in ultrascaled SNWTs. The optimized LER parameters are also given for the nanowire LER design with acceptable performance variation and suppressed mean value degradation in SNWTs.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000283446600011&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; SCI(E); EI; 12; ARTICLE; 11; 2864-2871; 57
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/152658]
专题	信息科学技术学院工学院
推荐引用方式 GB/T 7714	Yu, Tao,Wang, Runsheng,Huang, Ru,et al. Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs[J]. ieee电子器件汇刊,2010.
APA	Yu, Tao,Wang, Runsheng,Huang, Ru,Chen, Jiang,Zhuge, Jing,&Wang, Yangyuan.(2010).Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs.ieee电子器件汇刊.
MLA	Yu, Tao,et al."Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs".ieee电子器件汇刊 (2010).