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	A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination
	Li, Xuan; Chen, Ziyang; Zeng, Xuan; Lin, Zhiting; Liu, Changyong; Wu, Xiulong; Zhao, Qiang; Chen, Junning; Peng, Chunyu; Hu, Xiangdong
刊名	IEICE Electronics Express
	2018
卷号	Vol.15 No.15
ISSN号	1349-2543
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2202712
专题	安徽大学
作者单位	1.200433, China 2.230601, China 3.Shanghai High Performance Integrated Circuit Design Center, Shanghai 4.) School of Electronics and Information Engineering, Anhui University, Hefei 5.State Key Laboratory of ASIC & System, Department of Microelectronics, Fudan University, Shanghai
推荐引用方式 GB/T 7714	Li, Xuan,Chen, Ziyang,Zeng, Xuan,et al. A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination[J]. IEICE Electronics Express,2018,Vol.15 No.15.
APA	Li, Xuan.,Chen, Ziyang.,Zeng, Xuan.,Lin, Zhiting.,Liu, Changyong.,...&Hu, Xiangdong.(2018).A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.IEICE Electronics Express,Vol.15 No.15.
MLA	Li, Xuan,et al."A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination".IEICE Electronics Express Vol.15 No.15(2018).

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