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	A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process
	Liu,Changyong; Guan,Lijun; Chen,Junning; Li,Zhi; Peng,Chunyu; Wu,Xiulong; Lin,Zhiting
刊名	IEEE JOURNAL OF SOLID-STATE CIRCUITS ; IEEE JOURNAL OF SOLID-STATE CIRCUITS
	2017
卷号	Vol.52 No.3页码:669-677
关键词	DESIGN
ISSN号	0018-9200
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2200590
专题	安徽大学
作者单位	1.Semicond Mfg Int Corp, Shanghai 201210, Peoples R China 2.Anhui Univ, Sch Elect & Informat Engn, Hefei 230601, Peoples R China
推荐引用方式 GB/T 7714	Liu,Changyong,Guan,Lijun,Chen,Junning,et al. A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE JOURNAL OF SOLID-STATE CIRCUITS,2017,Vol.52 No.3:669-677.
APA	Liu,Changyong.,Guan,Lijun.,Chen,Junning.,Li,Zhi.,Peng,Chunyu.,...&Lin,Zhiting.(2017).A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.IEEE JOURNAL OF SOLID-STATE CIRCUITS,Vol.52 No.3,669-677.
MLA	Liu,Changyong,et al."A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process".IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.52 No.3(2017):669-677.

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