A parasitic extraction method of VLSI interconnects for pre-route timing analysis

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	A parasitic extraction method of VLSI interconnects for pre-route timing analysis
	Gong, Weibing; Yu, Wenjian; Lü, Yongqiang; Tang, Qiming; Zhou, Qiang; Cai, Yici
	2010
会议名称	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
会议日期	July 28, 2010 - July 30, 2010
会议地点	Chengdu, China
关键词	VLSI circuits Bioinformatics Digital libraries Electric batteries Heterojunction bipolar transistors Product design Time measurement Trees (mathematics) Capacitance extraction Commercial tools Computational speed Industrial design Parasitic extraction Parasitics RC trees Standard cell Timing Analysis VLSI design VLSI interconnects
页码	871-875
通讯作者	Yu, W. (yu-wj@tsinghua.edu.cn)
会议录	2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
会议录出版地	Piscataway
学科主题	Special Purpose Instruments;Production Engineering; Information Science;Electric Batteries
语种	英语
内容类型	会议论文
源URL	[http://ir.lzu.edu.cn/handle/262010/185073]
专题	数学与统计学院_会议论文
推荐引用方式 GB/T 7714	Gong, Weibing,Yu, Wenjian,Lü, Yongqiang,et al. A parasitic extraction method of VLSI interconnects for pre-route timing analysis[C]. 见:2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010. Chengdu, China. July 28, 2010 - July 30, 2010.