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	Design of PCI-X interface for high speed network security co-processor
	Zhu Ying ; Bai Guo-qiang ; Chen Hong-yi
	2010-10-12 ; 2010-10-12
关键词	Practical Experimental/ computer networks coprocessors cryptographic protocols peripheral interfaces system-on-chip/ PCI-X interface high speed network security coprocessor algorithm engines PCI-X bus interface SoC chip/ B6120D Cryptography B6150M Protocols B6210L Computer communications B1265F Microprocessors and microcomputers C5610P Peripheral interfaces C6130S Data security C5130 Microprocessor chips C5620 Computer networks and techniques
中文摘要	The method to design PCI-X interface for high speed network security co-processor is introduced, which uses two protocols such as IPSec and SSL/TLS protocols to optimize the system, and deploys different kinds of algorithm engines. The co-processor uses PCI-X bus interface and SoC chip with higher performance, which meets the requirement of both PCI-X bus protocol and the internal data transfers of co-processor. Experimental results show this method is feasible.
语种	中文
出版者	Editorial Board of Computer Engineering ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/82168]
专题	清华大学
推荐引用方式 GB/T 7714	Zhu Ying,Bai Guo-qiang,Chen Hong-yi. Design of PCI-X interface for high speed network security co-processor[J],2010, 2010.
APA	Zhu Ying,Bai Guo-qiang,&Chen Hong-yi.(2010).Design of PCI-X interface for high speed network security co-processor..
MLA	Zhu Ying,et al."Design of PCI-X interface for high speed network security co-processor".(2010).

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