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	Design and implement of RS485 high speed data communications protocol
	Geng Lizhong ; Wang Peng ; Ma Cheng ; Jia Huibo
	2010-10-12 ; 2010-10-12
关键词	Practical/ field programmable gate arrays intersymbol interference peripheral interfaces protocols signal detection signal sampling synchronisation/ high-speed baseband communication RS485 communication protocol inter symbol interference ISI bit synchronization signal detection scheme signal sampling field programmable gate array FPGA/ B6150M Protocols B6140M Signal detection B7210E Instrumentation buses and protocols
中文摘要	This paper describes a RS485 communications protocol for high-speed baseband communications. The inter symbol interference (ISI) is reduced by an efficient bit synchronization signal detection scheme. Sampling begins at the beginning of the input signals to get exact digital results. The frame synchronization uses 8 B/10 B coding and guarantees bit synchronization. The protocol was implemented on a field programmable gate array (FPGA) with test results indicating that the protocol achieves 14. 5 Mb/s along a 220 meters line.
语种	中文
出版者	Tsinghua University Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/80434]
专题	清华大学
推荐引用方式 GB/T 7714	Geng Lizhong,Wang Peng,Ma Cheng,et al. Design and implement of RS485 high speed data communications protocol[J],2010, 2010.
APA	Geng Lizhong,Wang Peng,Ma Cheng,&Jia Huibo.(2010).Design and implement of RS485 high speed data communications protocol..
MLA	Geng Lizhong,et al."Design and implement of RS485 high speed data communications protocol".(2010).

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