| 二次Booth编码的大数乘法器设计 | |
| 颜晓东 ; 李树国 ; YAN Xiaodong ; LI Shuguo | |
| 2010-06-09 ; 2010-06-09 | |
| 关键词 | 乘法器 Booth编码 模乘 RSA算法 multiplier secondary Booth recoding module multiplication Rivest Shamir and Adleman algorithm TN79 |
| 其他题名 | Algorithm and circuit design for secondary Booth encoded multiplier |
| 中文摘要 | 为了解决现有信息安全公钥签名算法存在的对大量模乘运算处理速度不快的问题,提出了一种高阶Booth编码的大数乘法器结构和二次编码的Booth 64线性变换式。二次编码既减少了部分积个数,也减少了高阶Booth编码预计算奇数倍的被乘数个数。基于此结构和编码,用Verilog代码设计了570×570b流水线乘法器。基于SMIC 0.18μm工艺,综合表明电路的关键路径延时为5.8 ns,芯片面积小于30mm2。可用于高性能的整数因子分解算法(RSA)2048 b、椭圆曲线算法(ECC)素数域512 b芯片的实现。; A common shortcoming of existing public-key cryptography algorithms is the computation of a large number of modulation multiplications.This paper describes a secondary Booth-64 algorithm for large integer multiplications,which recodes the traditional high radix Booth recoding.The algorithm accelerates the reduction of partial products and reduces the number of odd multiples of the multiplicand which need to be pre-computed.A 570×570 b secondary Booth encoded pipeline multiplier was designed using the SMIC 0.18 μm CMOS process by Verilog.The results show that the design achieves a 5.8 ns delay on the critical path with an area of no more than 30 mm2.The design improves the performance of advanced cryptographic systems such as the high-speed Rivest Shamir and Adleman algorithm 2 048 b chips and the Elliptic curve cryptography(ECC) gf(p) 512 b chips.; 国家“八六三”高技术项目(2006AA01Z418); 国家自然科学基金资助项目(60276016,60476015); 部委基金资助项目(GJ0061) |
| 语种 | 中文 ; 中文 |
| 内容类型 | 期刊论文 |
| 源URL | [http://hdl.handle.net/123456789/57001]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | 颜晓东,李树国,YAN Xiaodong,等. 二次Booth编码的大数乘法器设计[J],2010, 2010. |
| APA | 颜晓东,李树国,YAN Xiaodong,&LI Shuguo.(2010).二次Booth编码的大数乘法器设计.. |
| MLA | 颜晓东,et al."二次Booth编码的大数乘法器设计".(2010). |
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