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	A self-tuning, adaptive 1.9 GHz fractional-N/integer frequency synthesizer
	Huang Shui-long ; Wang Zhi-hua ; Ma Huai-nan
	2010-05-06 ; 2010-05-06
关键词	Practical/ circuit tuning CMOS integrated circuits counting circuits frequency synthesizers inductors modulators phase locked loops phase noise pulse circuits switched capacitor filters voltage-controlled oscillators/ self-tuning frequency synthesizer fractional-N frequency synthesizer phase-locked loop integer PLL digital tuning analog tuning phase noise adaptive loop Sigma Delta modulator programmable counter swallow pulse divider on-chip VCO bias filter technique differential inductor switched capacitor array voltage-controlled oscillator SMIC CMOS technology SpectreVerilog simulation 1.7 to 2.1 GHz 0.18 micron 1.8 V 100 kHz 600 kHz/ B1230B Oscillators B1250 Modulators, demodulators, discriminators and mixers B1270E Active filters and other active networks B1180 Time varying and switched networks B2570D CMOS integrated circuits B1260 Pulse circuits B1265B Logic circuits B2140 Inductors and transformers/ frequency 1.7E+09 to 2.1E+09 Hz size 1.8E-07 m voltage 1.8E+00 V frequency 1.0E+05 Hz frequency 6.0E+05 Hz
中文摘要	A self-tuning, adaptive 1.9 GHz fractional-N/integer PLL based frequency synthesizer is proposed in the paper. A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO. The adaptive loop is introduced for automatic adjustment of the loop bandwidth, which can quicken the locking process. Two operation modes (integer/fractional-N) are achieved by switching on/off the output signal of Sigma Delta modulator. Just a programmable counter is needed for the swallow pulse divider. The on-chip VCO achieves a low phase noise by utilizing a bias filter technique and a differential inductor, and a 1.7 GHz~2.1 GHz tuning range by a switched capacitor array. Based on 0.18 mu m 1.8 V SMIC CMOS technology, SpectreVerilog simulation shows that the frequency synthesizer has a 100 kHz loop bandwidth, a<15 mu s settling time, and the phase noise is lower than -123 dBc at 600 kHz offset.
语种	中文 ; 中文
出版者	Chinese Inst. Electron ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/10789]
专题	清华大学
推荐引用方式 GB/T 7714	Huang Shui-long,Wang Zhi-hua,Ma Huai-nan. A self-tuning, adaptive 1.9 GHz fractional-N/integer frequency synthesizer[J],2010, 2010.
APA	Huang Shui-long,Wang Zhi-hua,&Ma Huai-nan.(2010).A self-tuning, adaptive 1.9 GHz fractional-N/integer frequency synthesizer..
MLA	Huang Shui-long,et al."A self-tuning, adaptive 1.9 GHz fractional-N/integer frequency synthesizer".(2010).

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