QQ客服 官方微博 反馈留言

	A 12-bit 1.74-mW 20-MS/s DAC with Resisitor-string and Current- Steering Hybrid Architecture
	Bill Ma; Qinjin Huang; Fengqi Yu
	2015
会议名称	IEEE SOCC2015
会议地点	Beijing
英文摘要	This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current- steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined by a slew-rate-enhanced class AB output amplifier for high speed. Compared to resistor string DACs, current steering DACs, or resistor-capacitor hybrid DACs, the proposed DAC shows a better tradeoff between power and speed at low power application demanding a sampling clock between 1 MHz and 100 MHz. The prototype is a 12-bit DAC implemented in 0.18-μm CMOS technology with the worst measured DNL/INL of 6.38 LSB / 7.55 LSB. The analogue part power consumption is 1.24 mW and the digital part 0.5mW at 1.35-V power supply at 20-MS/s sampling rate. Its output is single-end buffered voltage with a range of 500 mV. The core area is 0.16 mm 2 .
收录类别	EI
语种	英语
内容类型	会议论文
源URL	[http://ir.siat.ac.cn:8080/handle/172644/7277]
专题	深圳先进技术研究院_医工所
作者单位	2015
推荐引用方式 GB/T 7714	Bill Ma,Qinjin Huang,Fengqi Yu. A 12-bit 1.74-mW 20-MS/s DAC with Resisitor-string and Current- Steering Hybrid Architecture[C]. 见:IEEE SOCC2015. Beijing.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。