A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

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	A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches
	Zhu Xubin ; Ni Weining ; Shi Yin
刊名	半导体学报
	2009
卷号	30 期号:5 页码:109-112
中文摘要	a fully-differential switched-capacitor sample-and-hold (s/h) circuit used in a 10-bit 50-ms/s pipeline analog-to-digital converter (adc) was designed and fabricated using a 0.35-μm cmos process. capacitor fliparound architecture was used in the s/h circuit to lower the power consumption. in addition, a gain-boosted operational transconductance amplifier (ota) was designed with a dc gain of 94 db and a unit gain bandwidth of 460 mhz at a phase margin of 63 degree, which matches the s/h circuit. a novel double-side bootstrapped switch was used, improving the precision of the whole circuit. the measured results have shown that the s/h circuit reaches a spurious free dynamic range (sfdr) of 67 db and a signal-to-noise ratio (snr) of 62.1 db for a 2.5 mhz input signal with 50 ms/s sampling rate. the 0.12 mm~2 s/h circuit operates from a 3.3 v supply and consumes 13.6 mw.
学科主题	微电子学
收录类别	CSCD
资助信息	national high technology research and development program of china
语种	英语
公开日期	2010-11-23
内容类型	期刊论文
源URL	[http://ir.semi.ac.cn/handle/172111/15763]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Zhu Xubin,Ni Weining,Shi Yin. A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches[J]. 半导体学报,2009,30(5):109-112.
APA	Zhu Xubin,Ni Weining,&Shi Yin.(2009).A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches.半导体学报,30(5),109-112.
MLA	Zhu Xubin,et al."A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches".半导体学报 30.5(2009):109-112.